The present invention relates to multiprocessor computer technology, and more particularly, to a masking circuit within a multiprocessor computer system for masking the contents of a first command status register, associated with a first processor, from the multiprocessor system until the contents of a second command status register, associated with a second processor, is executed.
In a multiprocessor computer system, when one processor attempts to locate desired data in its own cache, and fails to locate such data, it is necessary to attempt to locate the data in the cache of the other processor. If the data is not found in the cache of the other processor, it is necessary to retrieve the data from a main store. Occasionally, the data is found in the cache of the other processor. The one processor must utilize the desired data in the execution of an instruction.
For some instructions, the one processor may retrieve the data directly from the cache of the other processor, store the data in its own cache, and utilize the data in the execution of the instruction.
However, for other instructions, the one processor cannot retrieve the data directly from the cache of the other processor. It is therefore necessary to perform a flush operation. During the flush operation, the desired data is flushed from the cache of the other processor to the main store. The data is then utilized by the one processor in the execution of its instruction.
However, during the flush operation, the one processor may be attempting to execute a command. If the command may be classified as one of said other instructions, in view of the need to flush the desired data from the cache of the other processor to the main store prior to the execution of the command, it is necessary to mask the presence of the command, in the one processor, from the remainder of the multiprocessor system until the flush operation is complete. When the flush operation is complete, the mask, associated with the command, is released and the command is executed. However, if the command may not be classified as one of said other instructions, the presence of the command should not be masked from the remainder of the multiprocessor system and execution of the command should commence uninhibited.